As an M sequence generator capable of generating any desired M sequences under an external control against the period, pattern and phase of the M sequences and suitable for circuit integration, there is a circuit proposed in Japanese patent application No. 62-083033 filed Apr. 6, 1987 in the name of the assignee of the instant application. The circuit is shown in FIG. 6. The circuit has an additional advantage that a cascade connection enables an increase in the period of M sequences if necessary. In FIG. 6, SR.sub.1 through SR.sub.n denote flip-flops of a shift register, E.sub.1 through E.sub.n refer to exclusive logical sum (hereinafter called "EOR") gates, G.sub.1 through G.sub.n designate steering gates for supplying the flip-flops with an initial value, MUX 1 denotes a multiplexer for generating a three-state output, L.sub.1 through L.sub.5 denote latch circuits, AND.sub.0 through AND.sub.n refer to AND circuits, DE-MPX denotes a demultiplexer, and INV.sub.1 and INV.sub.2 denote inverters. FBCNT designates a signal for controlling enabled and disabled conditions of the three-state output, and L.sub.6 is a latch circuit for synchronizing the control of conditions of the three-state output with a signal STB used for initializing generation of M sequences. Further, CS denotes a chip select signal, LE is a latch enable signal, DAT.sub.0 through DAT.sub.n-1 are data, SEL.sub.0 and SEL.sub.1 are data select signals, FBO is a feedback input terminal, FBI is an input terminal into the initial stage of the steering gates, and PN is a code output.
Such an M sequence generator can be used in a cyclic redundancy check (CRC) generator check circuit in the field of digital signal error detection technologies. When the M sequence generator of FIG. 6 is used, the CRC generator check circuit is capable of changing its generator polynomials. As a circuit arrangement of such an M sequence generator, there are two different types, i.e., a simple-type shift register arrangement and a modular-type shift register arrangement. The instant invention is directed to a modular-type shift register arrangement. FIG. 7 shows an arrangement of a CRC generator check circuit using the M sequence generator of FIG. 6. As shown in FIG. 7, by connecting an external circuit to the M sequence generator of FIG. 6 which circuit includes an exclusive logical sum gate E.sub.CRC and an AND gate AND.sub.CRC, a known CRC generator check circuit is readily established.
Referring to FIG. 7, it is explained in detail how to arrange the CRC generator check circuit. Assume hereinbelow that the total number of steps n of the modular-type shift register (SR.sub.1 through SR.sub.n) is fixed to sixteen (16). In most cases, the total step number n of a modular-type shift register is fixed to 8, 16 or 32 for facilitating controls by a microcomputer, memory, etc.
In order to arrange a CRC generator check circuit, it is necessary to use in the exterior an exclusive logical sum gate E.sub.CRC for summing at mod. 2 the final stage output (CAS terminal) of a modular-type shift register with operated data of CRC (CRC IN) and use an AND gate AND.sub.CRC for controlling a feedback of the result of the operation of the exclusive logical sum gate E.sub.CRC to a feedback signal input (FBO terminal) of the M sequence generator. By obtaining an exclusive logical sum of the final stage output of the modular-type shift register and the operated data and by applying it to a predetermined stage of the modular-type shift register, a known division circuit, i.e. CRC generator check circuit, is established. Therefore, when logic "1" is entered in a control signal CRCCNT in FIG. 7, a division circuit is established. In this circuit, when the operated data is entered in the CRCIN terminal, a result of the division according to a generator polynomial is outputted from the CRCOUT terminal, and examination surpluses to be used for error detection remain in respective stages of the modular-type shift register. When the control signal CRCCNT is changed from logic "1" to logic "0", outputs of AND.sub.CRC and AND.sub.1 through AND.sub.n exhibit logic "0", and the modular-type shift register performs a shift register operation to shift the data in the original form to the next stage in response to a clock signal. As a result, respective bits of examination surpluses are obtained serially from the CRCOUT terminal.
Such a generator polynomial is set by entering suitable data in the latch 4 from data lines DAT.sub.0 through DAT.sub.n-1. The latch 1 is supplied with logic "0" from all the data lines DAT.sub.0 through DAT.sub.n-1 so that all elements of the modular-type shift register exhibit logic "0" before starting CRC operation. The FBCNT signal is fixed to logic "0", the output of the multiplexer MUX 1 is set in a high impedance condition, and the FBO terminal serves as a terminal exclusive for entering a feedback signal. The data setting process is shown in Table 1. For example, in order to set generator polynomials X.sup.16 +X.sup.12 +X.sup.5 +1 and X.sup.16 +X.sup.15 +X.sup.2 +1, data are set as shown in FIGS. 8(a) and 9(a), respectively. In this case, the division circuit becomes equivalent to FIGS. 8(b) and 9(b), respectively.
Referring to a time chart of FIG. 10, it is explained in what timing respective signals are inputted and outputted when the M sequence generator of FIG. 7 is used in the CRC generator check circuit. Data for initializing the modular-type shift register and for setting generator polynomials are first entered in the latch 1 and the latch 2 at a time-division from the data lines DAT.sub.0 through DAT.sub.n-1. An address of the latches is instructed by SEL.sub.0 through SEL.sub.1, the latches are enabled by LE, and data are set in respective latches.
TABLE 1 __________________________________________________________________________ Data Selector Data SEL 0 SEL 1 DAT 0 DAT 1 DAT 2 . . . DATm-1 DATm . . . DATn-2 DATn-1 __________________________________________________________________________ 0 0 A.sub.0 A.sub.1 A.sub.2 . . . A.sub.m-1 A.sub.m . . . A.sub.n-1 A.sub.n-1 A.sub.1 : initial value of the (i + 1)th step of the shift register. All are "0" in CRC operation. 1 0 B.sub.0 B.sub.1 B.sub.2 . . . B.sub.m-1 B.sub.m . . . B.sub.n-2 B.sub.n-1 B.sub.1 : count of a generator poly- nomial X.sup.1. The count of X.sup.n becomes "1" automatically. __________________________________________________________________________
After the data are set, the STB signal triggers the circuit to start CRC operation. Firstly, all elements of the modular-type shift register are initialized to logic "0" by the data of the latch 1 and the latch 2, and geneation multinomials are established. Subsequently, operated data CRC1 is entered. During entering the operated data, the control signal CRCCNT is fixed to logic "1", the shift register performs a function of the division circuit. At this time, an operation result CRC2 is outputted to CRCOUT. When input of the operated data is completed, examination surpluses remain in respective stages of the modular-type shift register. Immediately, the control signal CRCCNT is fixed to logic "0", and subsequently, bit outputs CRC3 of the examination surpluses are outputted serially from CRCOUT.
As described, it is certainly possible to establish a CRC generator check circuit capable of changing generator polynomials, using the prior art M sequence generator. However, since the order number (multiplicity) of a generator polynomial is determined by the number of stages of the modular-type shift register, it is not possible to change the order numbers of the generator polynomials in the prior art M sequence generator in which the terminal for connection to the aforegoing EX is fixed to the final stage of the modular-type shift register.